According to a well-known example investigation after this invention had been done, the following patent document 1 was reported as one relating to this invention. In this patent document 1, a memory comprising two power supplies, which supply a higher voltage to a memory cell than the surrounding, is disclosed. In this patent document 1, an applied voltage to a power supply line of a memory cell or a word line is stepped-up, and the conception is different from this invention described later.
[Patent document 1] JP-A 120882/1993
The development of semiconductor technology has been directed toward the miniaturization of elements. With finer element design rules it has become necessary to lower power supply voltage and the MOSFET threshold voltage. The above-mentioned lower MOSFET threshold voltage brings about an increase in leakage current flowing to a drain source of an off-state MOSFET. Therefore, a problem arises in a bit line (or data line) connecting a plurality of static type memory cells which comprise a MOSFET with a low threshold voltage, that is, the operation margin decreases because the difference between a memory current flowing in a selected memory cell and said leakage current flowing in the other non-selected memory cells. Thus, the present inventors investigated a way to maintain said operation margin by increasing the threshold voltage of a MOSFET comprised of a memory cell with finer elements and by decreasing a generated leakage current, resulting in creating the present invention.